THEALE, United Kingdom--(BUSINESS WIRE)--Sondrel, one of the world’s leading system-to-silicon IC design consultancies, will take part in three technical conferences organised by leading independent semiconductor pure play foundry, TSMC, aimed at senior engineers.

The China Symposium takes place in Shanghai on June 6^th. Register at http://www.e21mm.cn/TSMC2013_SH/. The European Technology Symposium will take place at the Sheraton Hotel, Amsterdam Airport, Netherlands on June 18^th starting at 9.30am, while the Israel Technology Workshop will be held at the Dan Accadia Hotel, Herzliya, Israel, on June 26^th, also starting at 9.30am.

Explained Sondrel’s CEO, Graham Curren: “This is an excellent opportunity for us to explain the full range of services that we offer to influential figures within our industry. Importantly, it also allows us to demonstrate our close relationship with TSMC, with whom we are a design centre alliance partner, and to discuss processes and our mixed signal design expertise.”

More details can be found at:

http://www.hwacomms.com/EU/TSMC2013/techsymposium/Exhibitor/index.html

About Sondrel

Established in 2002, Sondrel is one of the world’s leading system-to-silicon IC consultancies with the largest and most experienced consulting team in Europe, and with wide ranging expertise across all aspects of the design flow and all industry-standard EDA tool suits. The company’s capabilities cover the entire IC design spectrum from RTL design, though verification, emulation and DFT to physical implementation, and include power analysis and yield management. Sondrel is experienced in highly-complex digital, mixed signal, analogue, low power and wireless designs having completed over 200 designs at a range of process geometries down to 20nm, all of which were delivered right first time. With offices in the UK, USA, France, Italy, Israel, Sweden, Finland and China, Sondrel provides flexible services and methodology consulting to many of the world’s leading semiconductor companies, enabling them to improve chip performance and reduce timescales and costs.